The present invention relates to an information processor and an information processing system which are controlled by clock signals. More particularly, the present invention pertains to an information processor and an information processing system which are suitable for reducing the clock cycle in order to achieve a high-speed information processing operation.
A first type of conventional information processor controlled by a clock signal is shown in FIG. 2. The reference numeral 201 denotes a clock oscillator which delivers an original clock signal, while the numeral 202 denotes a clock generator which receives the original clock signal 211 and generates clock signals 212 required to control logic devices 203 to 206. The reference numeral 213 denotes means for interfacing the logic devices which are controlled by the clocks 212 so as to operate in timed relation to each other.
As the clocks 212 used to control logic devices, it is common practice to employ multi-phase clocks, generally two- or four-phase clocks, which are different in phase from each other. Examples of multi-phase clocks are shown in FIGS. 4 to 6. FIG. 4 shows so-called non-overlap two-phase clocks which have respective time intervals t1 and t2 during which both of the clocks are at a low level. FIG. 5 shows overlap clocks having a duty cycle of 50% which are substantially 90° out of phase with each other. FIG. 6 shows four-phase clocks having a relatively short pulse width which are substantially 90° out of phase with each other. These clocks are selected in accordance with the form of the logic circuit that constitutes each individual logic device, or with the logic device designing method.
These multi-phase clock signals are generated in the clock generator 202 on the basis of the clock 211 and distributed to the logic devices. No processing of clock signals is carried out in the logic devices. Exchange of data between the logic devices is effected synchronously with the clock signal 211.
The first problem of this prior art approach is that the multi-phase clock signals 212 must be distributed throughout the information processor. For this reason, the clock skew is usually increased, and the duty cycle of each clock signal is offset from the desired value. This problem is particularly serious when the machine cycle is improved, or reduced, in order to achieve a high-speed information processing operation and the frequency of the multi-phase clock signals 212 is raised. In other words, the greater part of the machine cycle must be spared for the clock skew. On the other hand, the advantage of this prior art approach is that, since one set of multiphase clock signals 212 are distributed throughout the information processor, exchange of data between the logic devices can be effected synchronously.
FIG. 3 shows a second type of conventional information processor that employs a clock signal. The reference numerals 301, 302 respectively denote clock oscillators, 311, 312 original clock signals, 303, 304 information processing units controlled by the clock signals 311, 312, respectively, and 313 an interface employed between the information processing units 303 and 304. This information processor comprises two information processing units which have their respective clock oscillators 301 and 302. A clock generator which processes an original clock signal to generate multi-phase clock signals such as those shown in FIGS. 4 to 6 is provided inside each information processing unit. Exchange of data between the information processing units 303 and 304 is effected asynchronously through the interface 313.
The arrangement of the second prior art approach is often found in microprocessor systems or the like. Each information processing unit corresponds to an LSI chip. The first problem of this prior art approach is that, since the two information processing units are controlled by two different clock signals, the information processing units must be interfaced asynchronously. An asynchronous interface needs to synchronize asynchronous signals and is therefore lower in speed than a synchronous interface. This problem is particularly serious when it is desired to produce a high-speed system in which exchange of data between information processing units is effected a great deal. However, this prior art approach has the advantage that the generation of clock signals is effected inside each information processing unit and, since the clock signals are distributed within one information processing unit, the clock skew can be minimized.
The second problem of this prior art approach is that it is necessary to supply a high-frequency original clock signal from the outside of each information processing unit in order to generate clock signals having a correct duty cycle, it is general practice to frequency-divide an original clock signal inside an information processing unit. Therefore, in the case where the input frequency is halved and the machine cycle is 40 MHz, an original clock signal of 80 MHz must be supplied externally. If a packaged LSI chip is considered to be used as a piece of hardware constituting an information processing unit, it is difficult to supply such an original clock signal from the outside. As the machine cycle is reduced, this problem becomes increasingly serious.
FIGS. 7 to 9 show in combination a third type of conventional information processor controlled by a clock signal. This system is discussed in “Asynchronous Approach for Clocking VLSI Systems” (IEEE Journal of Solid-State Circuits Vol. SC-17,pp. 51 56).
FIG. 7 shows the general arrangement of the prior art approach. The reference numeral 701 denotes an oscillator for delivering a clock signal 711, and 702 a frequency divider which divides the frequency of the clock signal 711 by N. Information processing units 703 and 704 are supplied with both clock signals 711 and 712. The numeral 713 denotes an interface circuit provided between the processing units 703 and 704.
FIG. 8 shows the internal arrangement of the information processing unit 703. The reference numeral 801 denotes a PLL (Phase Lock Loop) circuit which delays the clock signal 711 so that it is in a specific phase relation with the clock signal 712. The PLL circuit 801 delivers a clock signal 811 for controlling a logic device 802. On the other hand, the clock signal 712 is a clock obtained by dividing the frequency of the clock 711 by N, as described above, and it is employed to control an interface circuit 803. More specifically, the logic device inside the information processing unit is controlled by the high-speed clock signal 711, while the communication between the information processing units in which it takes a relatively long time to effect signal propagation is controlled by the low-speed clock 712.
In the case where two different kinds of clock signal are employed, exchange of data between the interface circuit 803 and the logic device 802 involves a problem which is known as metastability. This problem will be explained with reference to FIG. 9. Let us consider the case where data is delivered from the interface circuit 803 to the logic device 802. It is assumed that an edge trigger type flip-flop is used to constitute an interface 713. In the interface circuit 803, when the clock signal 712 rises from a low level, which is a first potential level, to a high level, which is a second potential level, data is taken in from the interface 713 and delivered to the logic device 802 through a signal bus 812. In the logic device 802, when the clock signal 811 rises from a low level to 4 high level, the data delivered is taken in. If the phase relationship between the clock signals 712 and 811 is shifted due to a skew such that the rise of the clock 712 overlaps the vicinity of the rise of the clock 811 (i.e., the portion denoted by the reference symbol tc in FIG. 9), the input of the flip-flop in the logic device is unstable when it is hit by the clock signal 811, resulting in the phenomenon that no output is determined in the flip-flop for a long period of time. This phenomenon is called metastability.
In order to avoid the above-described metastability, in this prior art, the PLL circuit 801 is inserted as shown in FIG. 8 to fix the phase relationship between the clock signals 711 and 712 as shown in FIG. 9.
The first problem of the third prior art approach is that the high-speed clock signal 711 must be supplied from the outside of the information processing unit. The second problem is that no consideration is given to the clock duty cycle used inside the information processing unit.
A fourth type of conventional information processor controlled by a clock signal, that is, “A 130 K-Gate CMOS Mainframe Chip Set” ISSCC 87, SESSION VIII, pp. 86–87, 1987, which is a semiconductor integrated circuit device having logic circuits controlled by clock signals, is shown in FIG. 42.
In FIG. 42, the reference numeral 1 denotes a semiconductor integrated circuit device, 2 a pad, 3 an input buffer, 201 to 203 first-stage clock buffers, 211 to 219 second-stage clock buffers, and 221 to 226 logic circuit blocks controlled by clock signals.
An external clock signal 10 input to the pad 2 is formed into an internal clock signal 11 through the input buffer 3. The clock signal 11 is distributed by the first-stage clock buffers 201 to 203 in the form of clock signals 231 to 233, and these signals are further distributed by the second-stage clock buffers 211 to 219 in the form of clock signals 241 to 249 to control the logic circuit blocks 221 to 226.
In the fourth prior art approach, logic circuit blocks which are present throughout a semiconductor integrated circuit device and which are controlled by clock signals are divided into a plurality of blocks and a clock buffer is provided for each of the divided logic circuit blocks to supply a clock signal thereto, thereby enabling a reduction in the load which is driven by each clock buffer. Accordingly, it is possible to reduce the delay in signal transmission from the reception of the external clock signal to the generation of the clock signal for controlling each internal logic circuit.
In the fourth prior art, logic circuit blocks on a semiconductor integrated circuit are divided into a plurality of blocks and a clock buffer is provided for each of the divided logic circuit blocks, as described above. More specifically, in the arrangement shown in FIG. 42, the clock signals 241 and 248 which control the logic circuit blocks 221 and 226, respectively, are formed from the internal clock signal 11 through the buffers 201, 211 and 203, 218, respectively. Thus, the clock signals for controlling the logic circuit blocks are supplied from the respective buffers which are different from each other, and therefore variations in delay time among the buffers due to the difference in driving capacity between the buffers, variations in load to be driven thereby, and variations in production of elements constituting the buffers result in a clock skew. An excessive clock skew may cause errors in exchange of signals between the logic circuit blocks.
A fifth type of conventional information processor controlled by a clock signal, that is, “A 15MIPS 32b Microprocessor” ISSCC 87, SESSION II, pp. 26–27, 1987, which is a semiconductor integrated circuit device having logic circuits controlled by clock signals, is shown in FIG. 43.
In FIG. 43, the same elements or portions as those in FIG. 42 are denoted by the same reference numerals. The numeral 4 denotes a clock internal buffer, 301 a clock driver, and 311 to 318 logic circuit blocks controlled by clock signals.
The external clock signal 10 input to the pad 2 is formed into an internal clock signal 11 through the input buffer 3. The clock signal 11 is formed into a clock signal 321 through the clock internal buffer 4 and then input to the clock driver 301, from which clock signals 322 are supplied to the logic circuit blocks 311 to 318 through a net-like signal wiring 322 laid throughout the semiconductor integrated circuit device to control the logic circuit blocks 311 to 318.
In the fifth prior art approach, all the logic circuit blocks which are present throughout the semiconductor integrated circuit device and which are controlled by clock signals are supplied with clock signals from a single clock driver. Therefore, it is possible to eliminate the phase shift, that is, skew, of the clock signals among the logic circuit blocks and hence eliminate errors in exchange of signals (data and information) between the logic circuit blocks.
In the fifth prior art approach, however, clock signals for controlling all the logic circuit blocks on the semiconductor integrated circuit device are supplied from a single clock driver as described above. Therefore, the clock driver 301 must drive a load of about 200 to 300 pF which consists of the net-like signal wiring 322 laid throughout the semiconductor integrated circuit device and the logic circuit blocks 311 to 318 as objects of control. Accordingly, the delay in activation of the clock driver 301 is increased. In addition, since the time required for the clock signal 322 to rise or fall is also increased, the current flowing through the logic circuits in the logic circuit blocks 311 to 318 which are activated in response to the clock signal 322 is increased, disadvantageously. Even if the driving capacity of the clock driver 301 is increased, the above-described problems cannot be solved because, if the high load (200 to 300 pF) is driven at high speed, a large noise is generated in power supply and grounding lines around the clock driver 301, causing a mal-operation.